1. Field of the Invention
This invention relates to a semiconductor integrated circuit composed of flip-flops, which receives data with the timing of a clock signal and retains it.
2. Description of the Related Art
Conventional data latch circuits are constructed as shown in FIG. 1A, for example. They are composed primarily of flip-flops using NOR gates. Specifically, the data latch circuit is made up of NOR gates G.sub.101 and G.sub.102 constituting a flip-flop, a NOR gate G.sub.201 serving as an input gate that transfers data D to one input terminal of the flip-flop under the control of clock CK supplied to one input terminal of this gate, and an inverter I.sub.101 that inverts clock CK and supplies it to the other input terminal of the flip-flop.
To increase the current driving capacity of the data latch, for example, an inverter buffer I.sub.102 is provided as an output buffer as shown FIG. 1B. In the FIG. 1B data latch circuit with the output buffer, data taken in on clock has to pass through three stages of gate G.sub.101, gate G.sub.102, and inverter buffer I.sub.102 before it reaches the output terminal. This delays the data transfer between the input and output in the data latch circuit.
FIG. 1C shows another conventional flip-flop circuit, which is composed of NOR gates G.sub.101 and G.sub.102 constituting a flip-flop stage, AND gates G.sub.501 and G.sub.502 serving as input gates, and inverter buffers I.sub.103 and I.sub.104 serving as output buffers. Like the FIG. 1B data latch circuit, this flip-flop circuit also has a data delay due to three gate stages. Data delay will be explained, referring to the timing chart in FIG. 2. Assume that while data output Q is in the "1" state and the inverse data output of Q, /Q is in the "0" state, data consisting of A="0" and /A="1" is supplied. Here, to cause the input data to appear at the output Q, it is necessary for data /A to cause the output node N.sub.102 of NOR gate G.sub.102 to change from "1" to "0", which then causes the output node N.sub.101 of NOR gate G.sub.101 to change from "0" to "1", thereby changing the output of inverter buffer I.sub.103 from "1" to "0". Therefore, data must pass through three gates, NOR gates G.sub.102 and G.sub.101 , and inverter buffer I.sub.103.
The same is true for D flip-flop circuits and the slave stage of master-slave flip-flop circuits.
As noted above, in various types of conventional flip-flop and data latch circuits, there is a delay introduced by three stages of gates from when data is supplied to the flip-flop stage and when it appears at the output terminal of the output buffer. Such a delay has been an obstacle to faster data processing.
For technical literature related to the present invention, reference may be made to Steven I. Long et al., "High Speed GaAs Integrated Circuits," Proceeding of The IEEE, Vol. 70, No. 1, January 1982, pp. 20-30 and Y. Kamatani et al.,"DIVIDE BY 128/129 5 mW 400 MHz BAND GaAs PRESCALER IC," IEEE, 1985, GaAs IC Symposium, pp. 179-182.